1. Technical Field
The present invention relates to data processing systems and, in particular, to bus usage and arbitration in a data processing system. Still more particularly, the present invention provides a method, apparatus, and program for locking device addresses to facilitate optimum usage of an inter-integrated circuit bus.
2. Description of Related Art
A bus is a common pathway, or channel, between multiple devices. The computer's internal bus is known as the local bus, or processor bus. This type of bus provides a parallel data transfer path between the CPU and main memory and to the peripheral buses. A 16-bit bus transfers two bytes at a time over 16 wires. Likewise, a 32-bit bus uses 32 wires to transfer four bytes of data at a time. The bus is comprised of two parts: the address bus and the data bus. Addresses are sent over the address bus to signal a memory location, and the data is transferred over the data bus to that location.
Various other types of buses are used in data processing systems. In particular, an Inter-Integrated Circuit (IIC) bus is an example of another type of bus used in a data processing system. An IIC bus, also referred to as an I2C bus, was developed by Koninklijke Philip's Electronics, also known as Philips Semiconductors. Details and specifications on the protocols for this bus are found in The I2C-Bus Specification, Version 2.1, January 2000. In this bus, one wire carries a clock signal, while another wire carries the data signal. This type of bus is used to provide interconnection between various devices, such as a flexible service processor (FSP), a memory, and a control panel. A flexible service processor is a processing unit that is used to initialize a data processing system. A FSP has its own boot code and operating system and may be connected to a number of input/output (I/O) devices.
In a complex embedded systems environment, a single IIC bus has several slave devices attached and multiple applications communicate with multiple end devices. In some cases, an application must access a device on the bus for a defined and continuous period of time. This may be achieved by placing a device soft lock on the bus usage or guarding the usage of the bus through a semaphore, until the application frees up the bus after transfer is complete.
One example of such a usage scenario is vital product data (VPD) collection or update on Squadrons. For read operations, the VPD application needs to access the Squadron electrically erasable programmable read only memory (SEEPROM), which in some cases may be of bigger memory size than the memory buffer size of the IIC controller hardware on the FSP cards. In such cases, the application needs to lock the bus until it reads all data on the SEEPROM chips, so that no other application can disrupt the operation by trying to access the same device on the same bus.
In the case of write operations, the VPD application may attempt to write, for example, 256 bytes. The memory chips may have an eight byte page write support. At the end of each page write, the end device goes into a write cycle (maximum 10 ms). The 256 byte write needs to be broken up into 32 eight-byte writes. After each of these 32 IIC write operations, there may be 10 ms idle bus time. The bus is locked by one such process even though there is idle bus time during the lock period, when other applications could possibly be using the bus to access other devices on the same bus.
Thus, the current arbitration mechanism of locking the bus creates a problem of bus hogging by one process. All other applications must wait until the application that has the lock frees the bus. Therefore, it would be advantageous to have an improved method, apparatus, and program instructions for device address locking to facilitate optimum usage of an inter-integrated circuit bus.